/* ------------------------------------------------------------------------------------------------------------------------ ---------------------------------------------------- Globaler Header --------------------------------------------------- **************************************************** iomx8.h ** V1.1 *************************************************** ------------------------------------------- Zur Definition der Register-Bits ------------------------------------------- ------------------------------------------------------------------------------------------------------------------------ Version..............: 1.1 Compiler.............: CodeVisionAVR Chip.................: ATmega88 Datum................: Juni 2009 Autor................: Alwin Lenck (ALE23) basierend auf dem Header iomx8.h von Udo Juerss ------------------------------------------------------------------------------------------------------------------------ Allgemeines: In dieser Header-Datei werden nur die Bits der Register definiert. Die Register selbst werden in der Header-Datei MEGA88.H des Mikrocontrollers ATmega88 definiert. Die Datei MEGA88.H wird hier mit #include zugefuegt. Die Auflistung der Register und deren Bits werden in der Reihenfolge der Register Summery des ATMEL-Manuals vorgenommen. Das heisst, dass die oberste Register-Adresse auch an der obersten Stelle erscheint. Ebenso werden die hoeherwertigen Bits jeweils als erstes genannt. Register ohne expliziter Bit-Nennung bzw. nicht belegte (reservierte) Bits werden hier nicht mehr erwaehnt. */ //---------------------------------------------------------------------------------------------------------------------- // Abfrage, ob diese Header-Datei bereits aufgerufen wurde. Wenn JA, dann alle Anweisungen ignorieren! //---------------------------------------------------------------------------------------------------------------------- #ifndef __IOMX8_H #define __IOMX8_H // Wenn NEIN, dann wird hier der Schalter gesetzt, dass zukuenftig // diese Header-Datei nicht noch einmal hinzugefuegt wird. //---------------------------------------------------------------------------------------------------------------------- // Header-Datei einfuegen //---------------------------------------------------------------------------------------------------------------------- #include // Zur Definition der externen I/O Register (absolut: 0x60 bis 0xFF), // der Special Function Register (SFR) mit den I/O-Register-Adressen // 0x00 bis 0x3F (entsprechend absolut: 0x20 bis 0x5F) sowie den // Interrupt Vectors Definitions //---------------------------------------------------------------------------------------------------------------------- // Register UCSR0C (USART MSPIM [Master SPI Mode] Control and Status Register 0 C) Adresse (0xC2) //---------------------------------------------------------------------------------------------------------------------- #define UMSEL01 BIT7 // USART Mode Select Bit1 #define UMSEL00 BIT6 // USART Mode Select Bit0 #define UPM01 BIT5 // Parity Mode Bit1 #define UPM00 BIT4 // Parity Mode Bit0 #define USBS0 BIT3 // Stop Bit Select #define UCSZ01 BIT2 // Character Size 0 Bit1 (kombiniert mit UCSR0B) #define UDORD0 BIT2 // Data Order (im SPI Mode) #define UCSZ00 BIT1 // Character Size 0 Bit0 (kombiniert mit UCSR0B) #define UCPHA0 BIT1 // Clock Phase (im SPI Mode) #define UCPOL0 BIT0 // Clock Polarity //---------------------------------------------------------------------------------------------------------------------- // Register UCSR0B (USART MSPIM Control and Status Register 0 B) Adresse (0xC1) //---------------------------------------------------------------------------------------------------------------------- #define RXCIE0 BIT7 // RX Complete Interrupt Enable 0 #define TXCIE0 BIT6 // TX Complete Interrupt Enable 0 #define UDRIE0 BIT5 // USART Data Register Empty Interrupt Enable n #define RXEN0 BIT4 // Receiver Enable n #define TXEN0 BIT3 // Transmitter Enable n #define UCSZ02 BIT2 // Character Size 0 Bit2 (kombiniert mit UCSR0C) #define RXB80 BIT1 // Receive Data Bit 8 0 #define TXB80 BIT0 // Transmit Data Bit 8 0 //---------------------------------------------------------------------------------------------------------------------- // Register UCSR0A (USART MSPIM Control and Status Register 0 C) Adresse (0xC0) //---------------------------------------------------------------------------------------------------------------------- #define RXC0 BIT7 // Receive Complete #define TXC0 BIT6 // Transmit Complete #define UDRE0 BIT5 // Data Registry Emty #define FE0 BIT4 // Frame Error #define DOR0 BIT3 // Data OverRun #define UPE0 BIT2 // Usart Parity error #define U2X0 BIT1 // Double the USART Transmission Speed #define MPCM0 BIT0 // Multiprocessor Communication Mode //---------------------------------------------------------------------------------------------------------------------- // Register TWAMR (TWI [Slave] Address Mask Register) Adresse (0xBD) //---------------------------------------------------------------------------------------------------------------------- #define TWAM6 BIT7 // TWI Address Mask Bit7 #define TWAM5 BIT6 // TWI Address Mask Bit6 #define TWAM4 BIT5 // TWI Address Mask Bit5 #define TWAM3 BIT4 // TWI Address Mask Bit4 #define TWAM2 BIT3 // TWI Address Mask Bit3 #define TWAM1 BIT2 // TWI Address Mask Bit2 #define TWAM0 BIT1 // TWI Address Mask Bit1 //---------------------------------------------------------------------------------------------------------------------- // Register TWCR (TWI Control Register) Adresse (0xBC) //---------------------------------------------------------------------------------------------------------------------- #define TWINT BIT7 // TWI Interrupt Flag #define TWEA BIT6 // TWI Enable Acknowledge Bit #define TWSTA BIT5 // TWI START Condition Bit #define TWSTO BIT4 // TWI STOP Condition Bit #define TWWC BIT3 // TWI Write Collision Flag #define TWEN BIT2 // TWI Enable Bit #define TWIE BIT0 // TWI Interrupt Enable //---------------------------------------------------------------------------------------------------------------------- // Register TWAR (TWI [Slave] Address Register) Adresse (0xBA) //---------------------------------------------------------------------------------------------------------------------- #define TWA6 BIT7 // TWI (Slave) Address Register Bit6 #define TWA5 BIT6 // TWI (Slave) Address Register Bit5 #define TWA4 BIT5 // TWI (Slave) Address Register Bit4 #define TWA3 BIT4 // TWI (Slave) Address Register Bit3 #define TWA2 BIT3 // TWI (Slave) Address Register Bit2 #define TWA1 BIT2 // TWI (Slave) Address Register Bit1 #define TWA0 BIT1 // TWI (Slave) Address Register Bit0 #define TWGCE BIT0 // TWI General Call Recognition Enable Bit //---------------------------------------------------------------------------------------------------------------------- // Register TWSR (TWI Status Rgister) Adresse (0xB9) //---------------------------------------------------------------------------------------------------------------------- #define TWS7 BIT7 // TWI Status Bit7 #define TWS6 BIT6 // TWI Status Bit6 #define TWS5 BIT5 // TWI Status Bit5 #define TWS4 BIT4 // TWI Status Bit4 #define TWS3 BIT3 // TWI Status Bit3 #define TWPS1 BIT1 // TWI Prescaler Bit1 #define TWPS0 BIT0 // TWI Prescaler Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register ASSR (Asynchronous Status Register) Adresse (0xB6) //---------------------------------------------------------------------------------------------------------------------- #define EXCLK BIT6 // Enable External Clock Input #define AS2 BIT5 // Asynchronous Timer/Counter2 #define TCN2UB BIT4 // Timer/Counter2 Update Busy #define OCR2AUB BIT3 // Output Compare Register2 Update Busy A #define OCR2BUB BIT2 // Output Compare Register2 Update Busy B #define TCR2AUB BIT1 // Timer/Counter Control Register2 Update Busy A #define TCR2BUB BIT0 // Timer/Counter Control Register2 Update Busy B //---------------------------------------------------------------------------------------------------------------------- // Register TCCR2B (Timer/Counter2 Control Register B) Adresse (0xB1) //---------------------------------------------------------------------------------------------------------------------- #define FOC2A BIT7 // Force Output Compare A #define FOC2B BIT6 // Force Output Compare B #define WGM22 BIT3 // Waveform Generation Mode Bit2 (kombiniert mit TCCR2A) #define CS22 BIT2 // Clock Select Bit2 #define CS21 BIT1 // Clock Select Bit1 #define CS20 BIT0 // Clock Select Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register TCCR2A (Timer/Counter Control Register A) Adresse (0xB0) //---------------------------------------------------------------------------------------------------------------------- #define COM2A1 BIT7 // Compare Match Output A Mode Bit1 #define COM2A0 BIT6 // Compare Match Output A Mode Bit0 #define COM2B1 BIT5 // Compare Match Output B Mode Bit1 #define COM2B0 BIT4 // Compare Match Output B Mode Bit0 #define WGM21 BIT1 // Waveform Generation Mode Bit1 (kombiniert mit TCCR2B) #define WGM20 BIT0 // Waveform Generation Mode Bit0 (kombiniert mit TCCR2B) //---------------------------------------------------------------------------------------------------------------------- // Register TCCR1C (Timer/Counter1 Control Register C) Adresse (0x82) //---------------------------------------------------------------------------------------------------------------------- #define FOC1A BIT7 // Force Output Compare for Channel A #define FOC1B BIT6 // Force Output Compare for Channel B //---------------------------------------------------------------------------------------------------------------------- // Register TCCR1B (Timer/Counter1 Control Register B) Adresse (0x81) //---------------------------------------------------------------------------------------------------------------------- #define ICNC1 BIT7 // Input Capture Noise Canceler #define ICES1 BIT6 // Input Capture Edge Select #define WGM13 BIT4 // Waveform Generation Mode Bit3 (kombiniert mit TCCR1A) #define WGM12 BIT3 // Waveform Generation Mode Bit2 (kombiniert mit TCCR1A) #define CS12 BIT2 // Clock Select Bit2 #define CS11 BIT1 // Clock Select Bit1 #define CS10 BIT0 // Clock Select Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register TCCR1A (Timer/Counter1 Control Register A) Adresse (0x80) //---------------------------------------------------------------------------------------------------------------------- #define COM1A1 BIT7 // Compare Output Mode for Channel A #define COM1A0 BIT6 // Compare Output Mode for Channel A #define COM1B1 BIT5 // Compare Output Mode for Channel B #define COM1B0 BIT4 // Compare Output Mode for Channel B #define WGM11 BIT1 // Waveform Generation Mode Bit1 (kombiniert mit TCCR1B) #define WGM10 BIT0 // Waveform Generation Mode Bit0 (kombiniert mit TCCR1B) //---------------------------------------------------------------------------------------------------------------------- // Register DIDR1 (Digital Input Disable Register 1) Adresse (0x7F) //---------------------------------------------------------------------------------------------------------------------- #define AIN1D BIT1 // AIN1 Digital Input Disable #define AIN0D BIT0 // AIN0 Digital Input Disable //---------------------------------------------------------------------------------------------------------------------- // Register DIDR0 (Digital Input Disable Register 0) Adresse (0x7E) //---------------------------------------------------------------------------------------------------------------------- #define ADC5D BIT5 // ADC5 Digital Input Disable Bit5 #define ADC4D BIT4 // ADC4 Digital Input Disable Bit4 #define ADC3D BIT3 // ADC3 Digital Input Disable Bit3 #define ADC2D BIT2 // ADC2 Digital Input Disable Bit2 #define ADC1D BIT1 // ADC1 Digital Input Disable Bit1 #define ADC0D BIT0 // ADC0 Digital Input Disable Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register ADMUX (ADC Multiplexer Selection Register) Adresse (0x7C) //---------------------------------------------------------------------------------------------------------------------- #define REFS1 BIT7 // Reference Selection Bit1 #define REFS0 BIT6 // Reference Selection Bit0 #define ADLAR BIT5 // ADC Left Adjust Result #define MUX3 BIT3 // Analog Channel Selection Bit3 #define MUX2 BIT2 // Analog Channel Selection Bit2 #define MUX1 BIT1 // Analog Channel Selection Bit1 #define MUX0 BIT0 // Analog Channel Selection Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register ADCSRB (ADC Control and Status Register B) Adresse (0x7B) //---------------------------------------------------------------------------------------------------------------------- #define ACME BIT6 // Analog Comparator Multiplexer Enable #define ADTS2 BIT2 // ADC Auto Trigger Source Bit2 #define ADTS1 BIT1 // ADC Auto Trigger Source Bit1 #define ADTS0 BIT0 // ADC Auto Trigger Source Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register ADCSRA (ADC Control and Status Register A) Adresse (0x7A) //---------------------------------------------------------------------------------------------------------------------- #define ADEN BIT7 // ADC Enable #define ADSC BIT6 // ADC Start Conversion #define ADATE BIT5 // ADC Auto Trigger Enable #define ADIF BIT4 // ADC ADC Interrupt Flag #define ADIE BIT3 // ADC ADC Interrupt Enable #define ADPS2 BIT2 // ADC Prescaler Select Bit2 #define ADPS1 BIT1 // ADC Prescaler Select Bit1 #define ADPS0 BIT0 // ADC Prescaler Select Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register TIMSK2 (Timer/Counter2 Interrupt Mask Register) Adresse (0x70) //---------------------------------------------------------------------------------------------------------------------- #define OCIE2B BIT2 // Timer/Counter2 Output Compare Match B Interrupt Enable #define OCIE2A BIT1 // Timer/Counter2 Output Compare Match A Interrupt Enable #define TOIE2 BIT0 // Timer/Counter2 Overflow Interrupt Enable //---------------------------------------------------------------------------------------------------------------------- // Register TIMSK1 (Timer/Counter1 Mask Register) Adresse (0x6F) //---------------------------------------------------------------------------------------------------------------------- #define ICIE1 BIT5 // Timer/Counter1, Input Capture Interrupt Enable #define OCIE1B BIT2 // Timer/Counter1, Output Compare B Match Interrupt Enable #define OCIE1A BIT1 // Timer/Counter1, Output Compare A Match Interrupt Enable #define TOIE1 BIT0 // Timer/Counter1, Overflow Interrupt Enable //---------------------------------------------------------------------------------------------------------------------- // Register TIMSK0 (Timer/Counter Interrupt Mask Register) Adresse (0x6E) //---------------------------------------------------------------------------------------------------------------------- #define OCIE0B BIT2 // Timer/Counter Output Compare Match B Interrupt Enable #define OCIE0A BIT1 // Timer/Counter0 Output Compare Match A Interrupt Enable #define TOIE0 BIT0 // Timer/Counter0 Overflow Interrupt Enable //---------------------------------------------------------------------------------------------------------------------- // Register EICRA (External Interrupt Control Register A) Adresse (0x69) //---------------------------------------------------------------------------------------------------------------------- #define ISC11 BIT3 // Interrupt Sense Control 1 Bit1 #define ISC10 BIT2 // Interrupt Sense Control 1 Bit0 #define ISC01 BIT1 // Interrupt Sense Control 0 Bit1 #define ISC00 BIT0 // Interrupt Sense Control 0 Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register PCICR (Pin Change Interrupt Control Register) Adresse (0x68) //---------------------------------------------------------------------------------------------------------------------- #define PCIE2 BIT2 // Pin Change Interrupt Enable 2 #define PCIE1 BIT1 // Pin Change Interrupt Enable 1 #define PCIE0 BIT0 // Pin Change Interrupt Enable 0 //---------------------------------------------------------------------------------------------------------------------- // Register PRR (Power Reduction Register) Adresse (0x64) //---------------------------------------------------------------------------------------------------------------------- #define PRTWI BIT7 // Power Reduction TWI #define PRTIM2 BIT6 // Power Reduction Timer/Counter2 #define PRTIM1 BIT3 // Power Reduction Timer/Counter0 #define PRTIM0 BIT5 // Power Reduction Timer/Counter1 #define PRSPI BIT2 // Power Reduction Serial Peripheral Interface #define PRUSART0 BIT1 // Power Reduction USART0 #define PRADC BIT0 // Power Reduction ADC //---------------------------------------------------------------------------------------------------------------------- // Register CLKPR (Clock Prescale Register) Adresse (0x61) //---------------------------------------------------------------------------------------------------------------------- #define CLKPCE BIT7 // Clock Prescaler Change Enable #define CLKPS3 BIT3 // Clock Prescaler Select Bit3 #define CLKPS2 BIT2 // Clock Prescaler Select Bit2 #define CLKPS1 BIT1 // Clock Prescaler Select Bit1 #define CLKPS0 BIT0 // Clock Prescaler Select Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register WDTCSR (Watchdog Timer Control Register) Adresse (0x60) //---------------------------------------------------------------------------------------------------------------------- #define WDIF BIT7 // Watchdog Interrupt Flag #define WDIE BIT6 // Watchdog Interrupt Enable #define WDP3 BIT5 // Watchdog Timer Prescaler 3 #define WDCE BIT4 // Watchdog Change Enable #define WDE BIT3 // Watchdog System Reset Enable #define WDP2 BIT2 // Watchdog Timer Prescaler 2 #define WDP1 BIT1 // Watchdog Timer Prescaler 1 #define WDP0 BIT0 // Watchdog Timer Prescaler 0 //---------------------------------------------------------------------------------------------------------------------- // Register SPMCSR (Store Program Memory Control and Status Register) Adresse (0x57) //---------------------------------------------------------------------------------------------------------------------- #define SPMIE BIT7 // SPM Interrupt Enable #define RWWSB BIT6 // Read-While-Write Section Busy #define RWWSRE BIT4 // Read-While-Write Section Read Enable #define BLBSET BIT3 // Boot Lock Bit Set #define PGWRT BIT2 // Page Write #define PGERS BIT1 // Page Erase #define SELFPRGEN BIT0 // Self Programming Enable //---------------------------------------------------------------------------------------------------------------------- // Register MCUCR (MCU Control Register) Adresse (0x55) //---------------------------------------------------------------------------------------------------------------------- #define BODS BIT6 // BOD Sleep #define BODSE BIT5 // BOD Sleep Enable #define PUD BIT4 // Pull-up Disable #define IVSEL BIT1 // Interrupt Vector Select #define IVCE BIT0 // Interrupt Vector Change Enable //---------------------------------------------------------------------------------------------------------------------- // Register MCUSR (MCU Status Register) Adresse (0x54) //---------------------------------------------------------------------------------------------------------------------- #define WDRF BIT3 // Watchdog System Reset Flag #define BORF BIT2 // Brown-out Reset Flag #define EXTRF BIT1 // External Reset Flag #define PORF BIT0 // Power-on Reset Flag //---------------------------------------------------------------------------------------------------------------------- // Register SMCR (Sleep Mode Control Register) Adresse (0x53) //---------------------------------------------------------------------------------------------------------------------- #define SM2 BIT3 // Sleep Mode Select Bit2 #define SM1 BIT2 // Sleep Mode Select Bit1 #define SM0 BIT1 // Sleep Mode Select Bit0 #define SE BIT0 // Sleep Enable //---------------------------------------------------------------------------------------------------------------------- // Register ACSR (Analog Comparator Control and Status Register) Adresse (0x50) //---------------------------------------------------------------------------------------------------------------------- #define ACD BIT7 // Analog Comparator Disable #define ACBG BIT6 // Analog Comparator Bandgap Select #define ACO BIT5 // Analog Comparator Output #define ACI BIT4 // Analog Comparator Interrupt Flag #define ACIE BIT3 // Analog Comparator Interrupt Enable #define ACIC BIT2 // Analog Comparator Input Capture Enable #define ACIS1 BIT1 // Analog Comparator Interrupt Mode Select #define ACIS0 BIT0 // Analog Comparator Interrupt Mode Select //---------------------------------------------------------------------------------------------------------------------- // Register SPSR (SPI Status Register) Adresse (0x4D) //---------------------------------------------------------------------------------------------------------------------- #define SPIF BIT7 // SPI Interrupt Flag #define WCOL BIT6 // Write COLlision Flag #define SPI2X BIT0 // Double SPI Speed Bit //---------------------------------------------------------------------------------------------------------------------- // Register SPCR (SPI Control Register) Adresse (0x4C) //---------------------------------------------------------------------------------------------------------------------- #define SPIE BIT7 // SPI Interrupt Enable #define SPE BIT6 // SPI Enable #define DORD BIT5 // Data Order #define MSTR BIT4 // Master/Slave Select #define CPOL BIT3 // Clock Polarity #define CPHA BIT2 // Clock Phase #define SPR1 BIT1 // SPI Clock Rate Select 1 #define SPR0 BIT0 // SPI Clock Rate Select 0 //---------------------------------------------------------------------------------------------------------------------- // Register TCCR0B (Timer/Counter Control Register B) Adresse (0x45) //---------------------------------------------------------------------------------------------------------------------- #define FOC0A BIT7 // Force Output Compare A #define FOC0B BIT6 // Force Output Compare B #define WGM02 BIT3 // Waveform Generation Mode Bit3 (kombiniert mit TCCR0A) #define CS02 BIT2 // Clock Select Bit2 #define CS01 BIT1 // Clock Select Bit1 #define CS00 BIT0 // Clock Select Bit0 //---------------------------------------------------------------------------------------------------------------------- // Register TCCR0A (Timer/Counter Control Register A) Adresse (0x44) //---------------------------------------------------------------------------------------------------------------------- #define COM0A1 BIT7 // Compare Match Output A Mode Bit1 #define COM0A0 BIT6 // Compare Match Output A Mode Bit0 #define COM0B1 BIT5 // Compare Match Output A Mode Bit1 #define COM0B0 BIT4 // Compare Match Output A Mode Bit0 #define WGM01 BIT1 // Waveform Generation Mode Bit1 (kombiniert mit TCCR0B) #define WGM00 BIT0 // Waveform Generation Mode Bit0 (kombiniert mit TCCR0B) //---------------------------------------------------------------------------------------------------------------------- // Register GTCCR (General Timer/Counter Control Register) Adresse (0x43) //---------------------------------------------------------------------------------------------------------------------- #define TSM BIT7 // Timer/Counter Synchronization Mode #define PSRASY BIT1 // Prescaler Reset Timer/Counter2 #define PSRSYNC BIT0 // Prescaler Reset //---------------------------------------------------------------------------------------------------------------------- // Register EECR (EEPROM Control Register) Adresse (0x3F) //---------------------------------------------------------------------------------------------------------------------- #define EEPM1 BIT5 // EEPROM Programming Mode Bit1 #define EEPM0 BIT4 // EEPROM Programming Mode Bit0 #define EERIE BIT3 // EEPROM Ready Interrupt Enable #define EEMPE BIT2 // EEPROM Master Write Enable #define EEPE BIT1 // EEPROM Write Enable #define EERE BIT0 // EEPROM Read Enable //---------------------------------------------------------------------------------------------------------------------- // Register EIMSK (External Interrupt Mask Register) Adresse (0x3D) //---------------------------------------------------------------------------------------------------------------------- #define INT1 BIT1 // External Interrupt Request 1 Enable #define INT0 BIT0 // External Interrupt Request 0 Enable //---------------------------------------------------------------------------------------------------------------------- // Register EIFR (External Interrupt Flag Register) Adresse (0x3C) //---------------------------------------------------------------------------------------------------------------------- #define INTF1 BIT1 // External Interrupt Request 1 Enable #define INTF0 BIT0 // External Interrupt Request 0 Enable //---------------------------------------------------------------------------------------------------------------------- // Register PCIFR (Pin Change Interrupt Flag Register) Adresse (0x3B) //---------------------------------------------------------------------------------------------------------------------- #define PCIF2 BIT2 // Pin Change Interrupt Flag 2 #define PCIF1 BIT1 // Pin Change Interrupt Flag 1 #define PCIF0 BIT0 // Pin Change Interrupt Flag 0 //---------------------------------------------------------------------------------------------------------------------- // Register TIFR2 (Timer/Counter2 Interrupt Flag Register) Adresse (0x37) //---------------------------------------------------------------------------------------------------------------------- #define OCF2B BIT2 // Output Compare Flag 2 B #define OCF2A BIT1 // Output Compare Flag 2 A #define TOV2 BIT0 // Timer/Counter2 Overflow Flag //---------------------------------------------------------------------------------------------------------------------- // Register TIFR1 (Timer/Counter1 Interrupt Flag Register) Adresse (0x36) //---------------------------------------------------------------------------------------------------------------------- #define ICF1 BIT5 // Timer/Counter1, Input Capture Flag #define OCF1B BIT2 // Timer/Counter1, Output Compare B Match Flag #define OCF1A BIT1 // Timer/Counter1, Output Compare A Match Flag #define TOV1 BIT0 // Timer/Counter1, Overflow Flag //---------------------------------------------------------------------------------------------------------------------- // Register TIFR0 (Timer/Counter0 Interrupt Flag Register) Adresse (0x35) //---------------------------------------------------------------------------------------------------------------------- #define OCF0B BIT2 // Timer/Counter0 Output Compare B Match Flag #define OCF0A BIT1 // Timer/Counter0 Output Compare A Match Flag #define TOV0 BIT0 // Timer/Counter0 Overflow Flag //---------------------------------------------------------------------------------------------------------------------- // Register PORTD (Port D Data Register) Adresse (0x2B) //---------------------------------------------------------------------------------------------------------------------- #define PORTD7 BIT7 // #define PORTD6 BIT6 // #define PORTD5 BIT5 // #define PORTD4 BIT4 // #define PORTD3 BIT3 // #define PORTD2 BIT2 // #define PORTD1 BIT1 // #define PORTD0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register DDRD (Port D Data Direction Register) Adresse (0x2A) //---------------------------------------------------------------------------------------------------------------------- #define DDD7 BIT7 // #define DDD6 BIT6 // #define DDD5 BIT5 // #define DDD4 BIT4 // #define DDD3 BIT3 // #define DDD2 BIT2 // #define DDD1 BIT1 // #define DDD0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register PIND (Port D Input Pins Address) Adresse (0x29) //---------------------------------------------------------------------------------------------------------------------- #define PIND7 BIT7 // #define PD7 BIT7 // #define PIND6 BIT6 // #define PD6 BIT6 // #define PIND5 BIT5 // #define PD5 BIT5 // #define PIND4 BIT4 // #define PD4 BIT4 // #define PIND3 BIT3 // #define PD3 BIT3 // #define PIND2 BIT2 // #define PD2 BIT2 // #define PIND1 BIT1 // #define PD1 BIT1 // #define PIND0 BIT0 // #define PD0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register PORTC (Port C Data Register) Adresse (0x28) //---------------------------------------------------------------------------------------------------------------------- #define PORTC6 BIT6 // #define PORTC5 BIT5 // #define PORTC4 BIT4 // #define PORTC3 BIT3 // #define PORTC2 BIT2 // #define PORTC1 BIT1 // #define PORTC0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register DDRC (Port C Data Direction Register) Adresse (0x27) //---------------------------------------------------------------------------------------------------------------------- #define DDC6 BIT6 // #define DDC5 BIT5 // #define DDC4 BIT4 // #define DDC3 BIT3 // #define DDC2 BIT2 // #define DDC1 BIT1 // #define DDC0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register PINC (Port C Input Pins Address) Adresse (0x26) //---------------------------------------------------------------------------------------------------------------------- #define PINC6 BIT6 // #define PC6 BIT6 // #define PINC5 BIT5 // #define PC5 BIT5 // #define PINC4 BIT4 // #define PC4 BIT4 // #define PINC3 BIT3 // #define PC3 BIT3 // #define PINC2 BIT2 // #define PC2 BIT2 // #define PINC1 BIT1 // #define PC1 BIT1 // #define PINC0 BIT0 // #define PC0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register PORTB (Port B Data Register) Adresse (0x25) //---------------------------------------------------------------------------------------------------------------------- #define PORTB7 BIT7 // #define PORTB6 BIT6 // #define PORTB5 BIT5 // #define PORTB4 BIT4 // #define PORTB3 BIT3 // #define PORTB2 BIT2 // #define PORTB1 BIT1 // #define PORTB0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register DDRB (Port B Data Direction Register) Adresse (0x24) //---------------------------------------------------------------------------------------------------------------------- #define DDB7 BIT7 // #define DDB6 BIT6 // #define DDB5 BIT5 // #define DDB4 BIT4 // #define DDB3 BIT3 // #define DDB2 BIT2 // #define DDB1 BIT1 // #define DDB0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Register PINB (Port B Input Pins Address) Adresse (0x23) //---------------------------------------------------------------------------------------------------------------------- #define PINB7 BIT7 // #define PB7 BIT7 // #define PINB6 BIT6 // #define PB6 BIT6 // #define PINB5 BIT5 // #define PB5 BIT5 // #define PINB4 BIT4 // #define PB4 BIT4 // #define PINB3 BIT3 // #define PB3 BIT3 // #define PINB2 BIT2 // #define PB2 BIT2 // #define PINB1 BIT1 // #define PB1 BIT1 // #define PINB0 BIT0 // #define PB0 BIT0 // //---------------------------------------------------------------------------------------------------------------------- // Mit #endif endet jede Header-Datei //---------------------------------------------------------------------------------------------------------------------- #endif